Scaling the dimensions of memory arrays and cells affect operational characteristics of memory technologies. In some memory technologies, a reduction in size of word lines or bit lines can increase the resistivity of those lines as the cross-sectional area of conductive paths is reduced also. The increased resistance of word lines or bit lines may produce a reduction of voltage (e.g., voltage drops) along those lines, for example, as a function of the amount of current conducted by memory cells to/from the word lines or bit lines in response to voltages for data operations being applied to the word lines and/or bit lines.
At least some conventional memory architectures, such as those including dynamic random access memory (“DRAM”) cells and Flash memory cells, typically include gates as part of metal oxide semiconductor (“MOS”) transistors or structures. The gates operate to open and close conductive paths between the word lines or bit lines and portions of the memory cells used as storage. When one of the conventional memory cells is un-selected, its gate is in an “off” mode of operation and conducts negligible to no current. The gate structures used in conventional memory architectures buffer the conventional memory cells from the affects of increased resistance of word lines or bit lines (e.g., high current densities that can damage array lines). The above-described memory architectures, while functional for their specific technologies, are not well suited to address the scaling down of memory array and cell dimensions to smaller geometries (e.g., sub 45 nm dimensions) for other memory technologies. Further, the use of gate-like structures (e.g., a select device or non-ohmic device—NOD) to govern the flow of current in conventional memory architectures and memory cells facilitate data retention of un-selected memory cells during memory cell access operations to selected memory cells, and, thus, are not well-suited to operate memory cells other than those operating with gate-like structures including but not limited to 1T1R, 1D1R, 2T1R, and 2D1R memory cells, for example.
There are continuing efforts to provide improved systems, integrated circuits, and methods that minimize one or more of the drawbacks associated with conventional techniques for facilitating data operations in scaled memory arrays and cells, including but not limited to discrete two-terminal re-writeable non-volatile memory elements disposed in one or more two-terminal memory arrays.
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